Ph.D. Research Project: Developing Non-Intrusive Hybrid Fault Tolerance Techniques to Detect Errors in Multiple Processors Systems

The use of fault-tolerance structures in multiple processors systems due to the fact that it is almost impossible to manufacture integrated circuits without any defect in nanometer technologies [1]. As a result, the use of fault tolerant methods is crucial to allow that circuits with some amount of defects still reach the market, increasing yield and the lifetime of a chip. A classical example comes from DRAM circuits, where defects are compensated by the use of spare rows and columns. With the technology introduced in the past decade, the number of expected defects in high-density circuits is increasing, and fault-tolerant techniques able to detect and correct multiple faults are very expensive, in terms of area, power and performance. Aiming at reducing the overhead cost, fault tolerance features should be turn on only in the exact location of defects. In this way, fault tolerance structures would not penalize the circuit in power and/or performance in case a fault is not present. Defects can have permanent effect, such as stuck-at, shortcut or open signals, or still show intermittent effects, like crosstalk between interconnection lines. For the above mentioned classes of defects, detection and diagnoses can be developed during manufacturing test, and off-line tests also can run during the life time of the circuit [2, 3, 4]. So, with the information of fault locations, a mechanism to deactivate a defective component and turn on a fault tolerance feature can be used. For example, in a multiple processor system, once a defect or failure has been detected in a microprocessor, the software application can be mapped on the remaining hardware components of a multiprocessor circuit [5]. Unfortunately, this simple deactivation approach cannot deal with faulty router or faulty link in the NoC, unless the NoC is modified to be able to adapt itself in the presence of faults. In this way, we propose methods to detect faults in multiple processors systems.